The present invention relates to a CMOS (Complementary Metal-oxide Semiconductor) type semiconductor device having a gate electrode of p type and n type conductive polycrystalline silicon and a method of manufacture thereof.
The current trend of the semiconductor device has been changed from a CMOS semiconductor device whose gate electrode is composed of only polycrystalline silicon containing an n-type impurity into the so-called dual gate CMOS semiconductor device in which the gate electrode of an n-channel MOS transistor is composed of polycrystalline silicon containing an n-type impurity and the gate electrode of a p-channel MOS transistor is composed of polycrystalline silicon containing a p-type impurity. This dual gate contains a silicon oxide film, a silicon nitride film or resist coated on the surface of the polycrystalline silicon except a target area. A target area (for example, n-type) impurity is implanted in the non-coated area with these films as a mask by means of the ion-implantation technique or the diffusion technique. After removing this mask materials, the surface of the polycrystalline silicon on the area having the above-mentioned impurity is covered with the similar mask materials. The impurity having the opposite conductive type (for example, p type) to the above-mentioned impurity is implanted in the non-covered area by means of the ion-implantation technique.
For dividing the polycrystalline area into an n+ and a p+ conductive areas, as mentioned above, a mask material is formed on a specific area in doping a target impurity, which needs two associative processes of forming a mask. It is thus necessary to perform each process of forming a mask film, doing photolithography, and dry-etching a mask film twice. It means that the dual gate CMOS semiconductor composed as above has more manufacturing steps than the CMOS semiconductor device composed of polycrystalline silicon containing only one conductive impurity. This brings about the lowering of a manufacturing yield and the rise of a manufacturing cost of the semiconductor device and therefore the rise of a product cost. Further, the slip of fitting the mask patterns may be brought about in dividing the n-type and the p-type areas in the photolithography process. Hence, the fitting allowance is required, which has been an obstacle to finning the element and enhancing the concentration of the semiconductor device.
On the other hand, the MOS transistor having as a component of a gate electrode polycrystalline silicon or amorphous silicon film containing boron has a shortcoming that by performing a high temperature annealing with respect to the MOS transistor after forming the gate electrode, the boron is diffused from the gate electrode into a gate oxide film, in a worse case, penetrates the gate oxide film and reaches the silicon substrate, thereby causing a threshold voltage of the transistor to shift from a design value. It has been reported that the annealing in a hydrogen atmosphere diffuses boron through the gate oxide film faster than the annealing in a nitrogen atmosphere. (IEEE Electron Device Let., Vol.17, No.11, pp497 to 499)
In order to enhance the integration of the semiconductor device, the need for development of an SAC (Self-aligned contact) technique has risen. This SAC technique is composed by covering the gate electrode with a silicon nitride film and a silicon oxide serving as an insulating film between a gate electrode and the upper metal layer for an interconnection on the silicon nitride. Then, a contact hole, which is served as connecting the source and the drain of the MOS type semiconductor device with the electrode wiring, is formed by the dry-etching technique. In this dry-etching technique, the process is conditioned in order to make the etching speed of the silicon oxide faster than that of the silicon nitride. As a result, if the deviation of the designed position of a contact hole to a gate electrode pattern is brought about in the photolithography process, no short takes place between the gate electrode and the source or the drain.
The silicon nitride film that is important to this SAC technique is generally formed by means of the CVD (Chemical Vapor Deposition). This silicon nitride film contains several percents to 20 percents of hydrogen. This hydrogen serves to accelerate leakage of boron contained in the polycrystalline silicon layer into the substrate. In an extreme case, the amount of boron to be leaked through the gate oxide film is made so large that the channel area n-type silicon substrate of the p-channel MOS transistor is inverted into the p-type one.
It is an object of the present invention to provide a dual gate CMOS type semiconductor device which is composed to simplify the process of doping an impurity into a polycrystalline silicon layer formed in the aforementioned dual gate CMOS, reduce the leakage of boron in the hydrogen-related process as much as possible, and thereby have a target threshold voltage.
In the MOS transistor having as a gate electrode an amorphous or polycrystalline silicon film containing boron, by performing a high temperature annealing in a hydrogen atmosphere for the transistor fabrication (for example, at a temperature of 950xc2x0 C. and for ten minutes), the threshold voltage Vth obtained in the case of performing an annealing in a nitrogen atmosphere at the same temperature and during the same interval is shifted from about 1.5 V to 2.0 V. This indicates that the accelerating effect of hydrogen on boron diffusion in a silicon oxide film may bring about leakage of boron from the gate electrode into the substrate.
It has been found by means of the secondary ion mass spectroscope (SIMS) that if the annealing in a nitrogen atmosphere is performed with respect to the surface of the polycrystalline silicon containing boron, coated with a metal nitride film such as tungsten nitride (WNx) and titanium nitride (TiNx), the boron doped in the polycrystalline silicon is segregated into the interface of the metal nitride film as shown in FIG. 2A. Even in the same structure, however, the annealing in a hydrogen atmosphere brings about diffusion of boron onto the substrate, thereby causing lots of boron to be leaked into the substrate through the gate oxide film.
If the annealing is performed in an atmosphere where several percents of vapor is added to hydrogen, as shown in FIG. 2C, it has been found that the boron contained in the silicon is segregated into the metal nitride interface like the annealing in a nitrogen atmosphere.
On the other hand, it has been found that phosphorus or arsenic used as an n-type impurity doped in polycrystalline silicon is segregated into the gate insulating film interface composed of silicon oxide on the lower layer and has a high concentration on the interface.
This phenomenon, in which the boron served as a p-type impurity contained in the polycrystalline silicon in the metal nitride film/polycrystalline silicon/gate insulating film structure has a different segregated interface from phosphorus or arsenic served as an n-type impurity contained therein, makes contribution to both simplifying the dual gate CMOS process and reducing leakage of boron at a time.
That is, at first, boron is contained on the overall surface of the polycrystalline silicon film and a material served as a mask for screening phosphorus or arsenic is coated on the surface outside of the target area. In this state, an n-type impurity such as phosphorus or arsenic is implanted onto the non-mask area by means of the ion-implantation technique or the diffusion technique. Then, the mask material is removed and then another layer such as a metallic nitride layer is formed in place. Next, the annealing is performed in a nitrogen atmosphere or a hydrogen atmosphere with vapor added thereto. As a result, boron is segregated on the metallic nitride interface in the area where boron and an n-type impurity are dually doped (for example, in the case of implanting 2xc3x971015/cm2 of boron or arsenic) and the concentration is made lower to (1xc3x971020/cm2) on the insulating film interface on the ground. On the other hand, arsenic is segregated onto the gate insulating film interface and thus is high in concentration (2xc3x971020/cm2). As a result, as shown in FIG. 1, the area in which phosphorus is contained is made to be an n-type one, while the other area includes a polycrystalline silicon gate electrode having a p-type conductive characteristic. That is, only one process for specifying a doping area makes it possible to form a dual gate and allow the boron in the polycrystalline silicon to be segregated onto the metallic nitride interface, thereby reducing the leakage of boron.